1. Field of the Invention
The present invention relates to a parallel type analog to digital (A/D) converter.
2. Description of the Related Art
FIG. 4 shows a conventional parallel type A/D converter. The parallel type A/D converter has: a comparing circuit array 11 comprising a plurality of comparing circuits in which an input signal 2 is commonly supplied to one input terminal of each of the comparing circuits and reference voltages of reference voltage generating means comprising a reference voltage 3 and a reference resistor array 10 are applied to the other input terminals; and a logic processing circuit 7 for obtaining a digital conversion output 8 by logically processing comparison outputs from the comparing circuit array 11.
In the above construction, for the comparison outputs of the comparators, all of the comparators whose reference voltages are higher than the input signal 2 generate the comparison outputs at the 0 level and all of the comparators whose reference voltages are lower than the input signal 2 generate the comparison outputs at the 1 level on the assumption that the comparator whose comparison voltage is closest to the input signal 2 is used as a boundary comparator. Therefore, if a logic processing circuit 7 executes a logic process such as an exclusive OR or the like of the comparison outputs of the adjacent comparators and supplies an output of the exclusive OR to an encoding circuit, the digital conversion output 8 can be obtained. Such a conventional parallel type A/D converter can execute the A/D conversion at the highest speed due to its parallel characteristic. For example, please refer to the following literature by Takemoto for such a conventional parallel type A/D converter.
(Takemoto et al., "A fully Parallel 10-Bit A/D Converter with Video Speed", IEEE J., Solid-State Circuits, Vol. SC-17, pp. 1133 to 1138, December, 1982)
However, in such a conventional parallel type A/D converter, a high voltage accuracy of the comparator is necessary as a resolution rises. For instance, in the case of the accuracy of 10 bits, a difference between the reference voltages of the adjacent comparators is equal to about 2 mV. Therefore, a comparison voltage accuracy of a fraction of such a differential voltage is required for each comparator. It is very difficult to realize such a voltage accuracy and a yield is remarkably deteriorated. Costs are increased. Sizes of electronic elements constructing the comparator are increased. An electric power consumption increases or a high frequency characteristic is deteriorated. Further, since the number of comparators which are connected to the input signals increases with an increase in resolution, an input capacitance increases. This makes it difficult to drive high frequency input signal. A Distoration is increase and conversion accuracy is deteriorated. Similarly, since the number of comparators which are connected to the reference resistor array increases, an increase in voltage drop by an input, bias current of the comparator causes the conversion accuracy to be remarkably deteriorated. In the conventional parallel type A/D converter, it is difficult to realize an A/D converter of a high accuracy for the above reasons.